Technical Field
The present invention generally relates to non-planar semiconductor structures and the fabrication thereof. More particularly, the present invention relates to reducing spacer undercut and short-channel effects in non-planar semiconductor structures from loss of isolation material during fabrication.
Background Information
In the conventional fabrication of non-planar semiconductor devices, such as FinFETs (non-planar field-effect transistors with “fin” shaped raised structures), the isolation material surrounding the fins, for example, Shallow Trench Isolation (STI) material, the STI material is eaten away during various processes. In some cases, enough of the STI material is lost that under-cut occurs beneath the gate spacer, such that an electrical short is created. In addition, the STI loss may be enough that a cavity created for source/drain epitaxy may be too deep, inducing the short-channel effect.
Thus, a need exists to reduce the occurrence of under-cut beneath spacers and the short-channel effect from STI loss during non-planar semiconductor fabrication.